Short Description
Are you in search for a new challenge? Are you equipped with forward looking spirit and experienced in digital design flows and tools?
Take the opportunity and join us as a Senior Design Verification Engineer:
Our offer:
- Competitive Salary & Benefits;
- Knowledge and support from more experienced engineers;
- Respect for your private life and your choices;
- All tools required for high performance in your field;
- Responsible approach, long term commitments, and stability;
Your role:
- Own verification of IP’s and SoC’s in prototype and SoC design environment;
- Establish functional and performance benchmarks;
- Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms;
- IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.
Your profile:
- Sound basics of system Verilog, and good experience in constrained Random and Coverage Driven Verification with UVM/OVM
- Experience in creating any UVC components or sequences is must
- Basic knowledge on at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification etc. Expertise in one protocol is a must for Senior and above.
- Should be comfortable in updating the existing verification environment for feature updates. (bring-up/Architect UVM based Test bench from Scratch is a strong plus)
- EDA simulation/debugging tools agnostic
- Good knowledge of Perl/TCL/Python scripting.
- Domain expertise on any one of these for senior and above: CPU processor/server, multimedia, automotive, Ethernet, Mobile
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